版本：v1.0.0
操作系统：rhel7.9、rhel8.10
更新时间：2026-10-31
icg2mux - integrated clock gate to data-gating MUX2 ECO icg2mux gen -lib <file.lib> -netlist <in.v> [-out eco.tcl] [-top <module>] [-icg <pattern>]... [-icg-file <list.txt>] [-mux-cell <cell>] [-report] [-gof <out.pl>] [-lec <out.do>] icg2mux apply -lib <file.lib> -netlist <in.v> -eco <eco.tcl> -out <out.v> [-top <module>] [-report] icg2mux slice -netlist <in.v> -top <module> -out <sub.v> # module + what it instantiates icg2mux libcheck -lib <file.lib> [-lib ...] [-verbose] # is this library usable? gen : plan the ECO and write an Innovus ECO TCL script apply : execute the ECO TCL script on the netlist and write the new netlist options: -lib liberty file, may be repeated -netlist gate level Verilog netlist -eco ECO script to apply (apply only) -out output file (eco.tcl for gen, netlist for apply) -top top module name (default: first module in the netlist) -mux-cell force a MUX2 cell name (gen only) -icg gen only: convert only clock gates matching this pattern (instance name, module/instance, gated net, wrapper cell or ICG cell; '*' and '?' wildcards), repeatable -icg-file gen only: file with one such pattern per line ('#' comments ok) -keep-unused apply only: keep modules that the ECO left uninstantiated (default: they are pruned from the output netlist) -report print the modified gates to stdout -verbose with -report: also list the unchanged gates and every changed register -gof gen only: also write a GOF LEC perl script for the result -lec gen only: also write a Conformal LEC dofile for the result