`timescale 1ns/1ns
module tb();

   reg        clk;
   reg	      rst_n;
   wire [3:0] cnt;

   initial
     begin
	clk = 1'b0;
	forever
	  #10 clk = ~clk;
     end

   initial
     begin
	rst_n = 1'b0;
	#23 rst_n = 1'b1;
     end

   initial
     begin
	$display("#---- start of simulation ----");
	repeat(20)
	  @(posedge clk);
	#20 $display("#---- end of simulation ----");
	$finish();
     end // initial begin

   initial
     begin
	$dumpfile("tb.vcd");
	$dumpvars(0, tb);
     end

   top dut
     (
      .clk   (clk),
      .rst_n (rst_n),
      .cnt   (cnt[3:0])
      );

endmodule // tb
