`timescale 1ns/1ns
module top
	(
	input wire       clk,
	input wire       rst_n,
	output reg [3:0] cnt
	);

	always@(posedge clk, negedge rst_n)
	if(!rst_n)
		cnt <= 4'd0;
	else if(cnt >= 4'd9)
		cnt <= 4'd0;
	else
		cnt <= cnt + 1'b1;

endmodule